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 INTEGRATED CIRCUITS
DATA SHEET
SAB9080 NTSC Picture-In-Picture (PIP) controller
Preliminary specification Supersedes data of 1999 Jan 05 File under Integrated Circuits, IC02 1999 Nov 12
Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
FEATURES * Double window Picture-In-Picture (PIP) in interlaced or non-interlaced mode at 8-bit resolution * Internal 1-Mbit DRAM * Three 8-bit Analog-to-Digital Converters (ADCs) (7-bit performance) with clamp circuit for each acquisition channel * One PLL which generates the line-locked clocks for the subchannel * One PLL which generates the line-locked clocks for the main and display channels * Three 8-bit Digital-to-Analog Converters (DACs) * Linear zoom in both horizontal and vertical directions for the subchannel * Linear zoom in horizontal direction for the main channel. GENERAL DESCRIPTION The SAB9080 is an NTSC PIP controller which can be used in double window applications. The SAB9080 inserts one or two live video signals with reduced size into another live video signal. The incoming video signals are expected to be analog baseband signals. QUICK REFERENCE DATA SYMBOL Supply VDDD VDDA IDDD IDDA PLL fclk(sys) Bloop tjitter system clock frequency loop bandwidth short-term stability damping factor peak-to-peak jitter for 64 s 1792 x fHSYNC - - - - 28 4 - 0.7 - - 4 - digital supply voltage analog supply voltage digital supply current analog supply current 3.0 3.0 - 140 3.3 3.3 50 165 3.6 3.6 - 210 PARAMETER CONDITIONS MIN. TYP.
SAB9080
The conversion to the digital environment is done on chip with ADCs. Processing and storage of the video data is done entirely in the digital domain. The conversion back to the analog domain is done by DACs. Internal clocks are generated by PLLs which lock on to the applied horizontal and vertical syncs. The main input channel is compressed horizontally by a factor of two and directly fed to the output. After compression, a horizontal expansion of two is possible for the main channel. The subchannel is also compressed horizontally by a factor of two but stored in memory before it is fed to the outputs.
MAX.
UNIT
V V mA mA
MHz kHz ns
ORDERING INFORMATION TYPE NUMBER SAB9080H PACKAGE NAME QFP100 DESCRIPTION plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm VERSION SOT317-2
1999 Nov 12
2
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SU SV SY Vbias(SA) Vref(T)(SA) Vref(B)(SA) SHSYNC SVSYNC
BLOCK DIAGRAM
Philips Semiconductors
VSSA(MA) VDDA(DA) VDDD(DA) VSSD(P1) VDDD(RP) VSSD(RL) VDDD(RM) VDDD(P2)
VDDA(MF) VDDA(MA) VSSA(DA) VSSD(DA) VDDD(P1) VDDD(RL) VSSD(RM) VSSD(RP) VSSD(P2) 3 79 81 83 84 82 80 CLAMP AND ADC HORIZONTAL AND VERTICAL FILTER 4 5 6 7 14 15 16 17 20 39 40 41 42 61 64 65
handbook, full pagewidth
NTSC Picture-In-Picture (PIP) controller
VSSD(D) VDDA(SA) VDDA(SF) VDDD(SA) VDDD(D) VSSA(SA) VSSD(SA) 66 67 76 77 78 85 86 8 10 12 DAC AND BUFFER 9 11 13 DY DV DU Vbias(DA) Vref(T)(DA) Vref(B)(DA)
87 72 PLL AND CLOCK GENERATOR LINE MEMORY INTERNAL DRAM DISPLAY CONTROL
69 68
PKOFF FBL VSSD(T1) and VSSD(T2) VSSD(T3) VSSD(T4) to VSSD(T7) VSSD(T8) and VSSD(T9) DCLK TC T5 to T0
18, 19
3
MU MY MV Vbias(MA) Vref(T)(MA) Vref(B)(MA) DHSYNC DVSYNC
2 98 100 97 99 1 CLAMP AND ADC HORIZONTAL FILTER
2 30
SAB9080
4
48 to 51
62, 63
94 70 PLL AND CLOCK GENERATOR 19 89 VDDA(SP) 90 91 92 95 96 21 to 29, 31, 52 to 60 n.c. POR 75 74 73 88 T6 SCL 93 T7 44 TM 43 45 46 47 I2C-BUS CONTROL TEST CONTROL
71 38 32 to 37 6
Preliminary specification
MGM808
VSSA(DP)
VDDD(MA) VSSD(MA)
SDA
TCBD TCLK
TCBR
SAB9080
VSSA(SP)
VDDA(DP)
TCBC
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
PINNING SYMBOL Vref(B)(MA) MU VDDA(MF) VSSA(MA) VDDA(MA) VDDA(DA) VSSA(DA) DY Vbias(DA) DV Vref(T)(DA) DU Vref(B)(DA) VDDD(DA) VSSD(DA) VSSD(P1) VDDD(P1) VSSD(T1) VSSD(T2) VDDD(RP) n.c. VSSD(T3) n.c. T5 T4 T3 T2 T1 T0 TC VDDD(RL) VSSD(RL) VSSD(RM) VDDD(RM) TCLK TM TCBD TCBC TCBR VSSD(T4) to VSSD(T7) 1999 Nov 12 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 to 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 to 51 TYPE I/O I S S S S S O I/O O I/O O I/O S S S S S S S - S - I/O I/O I/O I/O I/O I/O I S S S S I I I I I S DESCRIPTION analog bottom reference voltage for main channel ADCs analog U input for main channel analog supply voltage for main channel front-end buffers analog ground for main channel ADCs analog supply voltage for main channel ADCs analog supply voltage for DACs analog ground for DACs analog Y output of DAC input/output analog bias reference voltage for DACs analog V output of DAC input/output analog top reference voltage for DACs analog U output of DAC analog bottom reference voltage for DACs digital supply voltage for DACs digital ground for DACs digital ground for periphery digital supply voltage for periphery digital ground for test digital ground for test digital supply voltage for memory periphery not connected digital ground for test not connected test data input/output bit 5 (CMOS levels) test data input/output bit 4 (CMOS levels) test data input/output bit 3 (CMOS levels) test data input/output bit 2 (CMOS levels) test data input/output bit 1 (CMOS levels) test data input/output bit 0 (CMOS levels) test control input (CMOS levels) digital supply voltage for memory logic digital ground for memory logic digital ground for memory core digital supply voltage for memory core test clock input (CMOS levels) test mode input (CMOS levels) test control block data input (CMOS levels) test control block clock input (CMOS levels) test control block reset input (CMOS levels) digital ground for test 4
SAB9080
Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
SAB9080
SYMBOL n.c. VSSD(RP) VSSD(T8) and VSSD(T9) VDDD(P2) VSSD(P2) VSSD(D) VDDD(D) FBL PKOFF DVSYNC DCLK SVSYNC SCL SDA POR VDDA(SA) VSSA(SA) VDDA(SF) SU Vref(B)(SA) SV Vref(T)(SA) SY Vbias(SA) VSSD(SA) VDDD(SA) SHSYNC T6 VDDA(SP) VSSA(SP) VSSA(DP) VDDA(DP) T7 DHSYNC VDDD(MA) VSSD(MA) Vbias(MA) MY Vref(T)(MA) MV
PIN 52 to 60 61 62 and 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
TYPE - S S S S S S O O I I I I/O I/O I S S S I I/O I I/O I I/O S S I I/O S S S S I/O I S S I/O I I/O I not connected
DESCRIPTION digital ground for memory periphery digital ground for test digital supply voltage for periphery digital ground for periphery digital ground for digital core digital supply voltage for digital core fast blanking control signal output (CMOS levels; +5 V tolerant) peak off control signal output (CMOS levels; +5 V tolerant) vertical sync display channel input (CMOS levels; +5 V tolerant) test clock input (28 MHz; CMOS levels) vertical sync for subchannel input (CMOS levels; +5 V tolerant) input/output serial clock (I2C-bus; CMOS levels; +5 V tolerant) input/output serial data/acknowledge output (I2C-bus; +5 V tolerant) power-on reset input (CMOS levels; pull-up resistor connected to VDD) analog supply voltage for subchannel ADCs analog ground for subchannel ADCs analog supply voltage for subchannel front-end buffers and clamps analog U input for subchannel input/output analog bottom reference voltage for subchannel ADCs analog V input for subchannel input/output analog top reference voltage for subchannel ADCs analog Y input for subchannel analog bias reference voltage for subchannel ADCs digital ground for subchannel ADCs digital supply voltage for subchannel ADCs horizontal sync input for subchannel (Vi < VSHSYNC) test data input/output bit 7 (CMOS levels) analog supply voltage for subchannel PLL analog ground for subchannel PLL analog ground for display channel PLL analog supply voltage for display channel PLL test data input/output bit 6 (CMOS levels) horizontal sync input for display channel (Vi < VDHSYNC) digital supply voltage for main channel ADCs digital ground for main channel ADCs analog bias reference voltage for main channel ADCs analog Y input for main channel analog top reference voltage for main channel ADCs analog V input for main channel
1999 Nov 12
5
Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
SAB9080
99 Vref(T)(MA)
97 Vbias(MA) 96 VSSD(MA)
92 VDDA(DP)
86 VDDD(SA) 85 VSSD(SA)
89 VDDA(SP)
91 VSSA(DP)
90 VSSA(SP)
100 MV
84 Vbias(SA)
94 DHSYNC
87 SHSYNC
handbook, full pagewidth
82 Vref(T)(SA)
95 VDDD(MA)
98 MY
83 SY
Vref(B)(MA) MU VDDA(MF) VSSA(MA) VDDA(MA) VDDA(DA) VSSA(DA) DY Vbias(DA)
81 SV 80 Vref(B)(SA) 79 SU 78 VDDA(SF) 77 VSSA(SA) 76 VDDA(SA) 75 POR 74 SDA 73 SCL 72 SVSYNC 71 DCLK 70 DVSYNC 69 PKOFF 68 FBL 67 VDDD(D) 66 VSSD(D) 65 VSSD(P2) 64 VDDD(P2) 63 VSSD(T9) 62 VSSD(T8) 61 VSSD(RP) 60 n.c. 59 n.c. 58 n.c. 57 n.c. 56 n.c. 55 n.c. 54 n.c. 53 n.c. 52 n.c. 51 VSSD(T7) VSSD(T6) 50
MGM809
93 T7
1 2 3 4 5 6 7 8 9
DV 10 Vref(T)(DA) 11 DU 12 Vref(B)(DA) 13 VDDD(DA) 14 VSSD(DA) 15 VSSD(P1) 16 VDDD(P1) 17 VSSD(T1) 18 VSSD(T2) 19 VDDD(RP) 20 n.c. 21 n.c. 22 n.c. 23 n.c. 24 n.c. 25 n.c. 26 n.c. 27 n.c. 28 n.c. 29 VSSD(T3) 30 n.c. 31 T5 32 T4 33 T3 34 T2 35 T1 36 T0 37 TC 38 VDDD(RL) 39 VSSD(RL) 40 VSSD(RM) 41 VDDD(RM) 42 TCLK 43 TM 44 TCBD 45 TCBC 46 TCBR 47 VSSD(T4) 48 VSSD(T5) 49
SAB9080
Fig.2 Pin configuration.
1999 Nov 12
6
88 T6
Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
FUNCTIONAL DESCRIPTION Acquisition The internal pixel rate is 28 MHz for the Y, U and V channels. It is expected that the bandwidth of the input signals will be limited to 4.5 MHz for the Y input and 1.125 MHz for the U and V inputs. Inset synchronisation is achieved via the acquisition HSYNC and VSYNC pins of the main channel. The display is driven by the main channel clock. PIP modes
SAB9080
The starting-point of the acquisition can be controlled with the acquisition fine positioning added to a system constant. With a nominal input 1792 x fHSYNC and standard NTSC signals, 1408 samples (active video) are acquired and processed by the SAB9080. Here, the nominal input fHSYNC results in a nominal system clock frequency of 1792 x fHSYNC (approximately 28 MHz).
handbook, full pagewidth
SUB
MAIN
SUB
SUB
MAIN
MGM810
MAIN
REPLAY
Fig.3 PIP modes.
I2C-bus description The I2C-bus provides bidirectional 2-line communication between different ICs. The SDA line is the serial data line and the SCL the serial clock line. Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. The SAB9080 has the I2C-bus address 2CH. Valid subaddresses are 00H to 18H; registers 15H to 18H are reserved for future extensions.
I2C-bus control is according to the I2C-bus protocol: first, a START sequence must be put on the I2C-bus. Then, the I2C-bus address of the circuit must be sent, followed by a subaddress. After this sequence, the data of the subaddresses must be sent. An auto-increment function gives the option of sending data of the incremented subaddresses until a STOP sequence is sent. Table 1 gives an overview of the I2C-bus addresses. The data bits that are not used should be set to zero.
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Table 1 Overview of I2C-bus addresses For a description of the various data bits, see the following pages. SUBADDRESS 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H to 18H DATA BYTES BIT 7 MPIPON SHBlow1 SVBlow BGVfp3 SDHfp7 SDVfp7 - - MAHfp3 SAVfp7 DUVPol MainFidPos7 SubFidPos7 BGOn BSel1 - I2CHold MDHfp7 MDVfp7 MHBlow - BIT 6 SPIPON SHBlow0 SVRed6 BGVfp2 SDHfp6 SDVfp6 - - MAHfp2 SAVfp6 DVSPol MainFidPos6 SubFidPos6 BOn BSel0 - SV1 MDHfp6 MDVfp6 SV2 VBwidth2 BIT 5 S1FLD SHRed5 SVRed5 BGVfp1 SDHfp5 SDVfp5 - - MAHfp1 SAVfp5 DFPol MainFidPos5 SubFidPos5 MFidPOn SBBrt1 SLSel5 SDSel5 MDHfp5 MDVfp5 MHRed5 VBwidth1 BIT 4 SFreeze SHRed4 SVRed4 BGVfp0 SDHfp4 SDVfp4 - - MAHfp0 SAVfp4 DHsync MainFidPos4 SubFidPos4 SFidPOn SBBrt0 SLSel4 SDSel4 MDHfp4 MDVfp4 MHRed4 VBwidth0 BIT 3 DNonint SHRed3 SVRed3 BGHfp3 SDHfp3 SDVfp3 - - SAHfp3 SAVfp3 SUVPol MainFidPos3 SubFidPos3 Prio - SLSel3 SDSel3 MDHfp3 MDVfp3 MHRed3 - BIT 2 PipMode2 SHRed2 SVRed2 BGHfp2 SDHfp2 SDVfp2 - - SAHfp2 SAVfp2 SVSPol MainFidPos2 SubFidPos2 AlgOff SBCol2 SLSel2 SDSel2 MDHfp2 MDVfp2 MHRed2 HBwidth2 BIT 1 PipMode1 SHRed1 SVRed1 BGHfp1 SDHfp1 SDVfp1 - - SAHfp1 SAVfp1 SFPol MainFidPos1 SubFidPos1 SFBlkPkOff1 SBCol1 SLSel1 SDSel1 MDHfp1 MDVfp1 MHRed1 HBwidth1 BIT 0 PipMode0 SHRed0 SVRed0 BGHfp0 SDHfp0 SDVfp0 - - SAHfp0 SAVfp0 SHsync MainFidPos0 SubFidPos0 SFBlkPkOff0 SBCol0 SLSel0 SDSel0 MDHfp0 MDVfp0 MHRed0 HBwidth0
1999 Nov 12 8
Philips Semiconductors
NTSC Picture-In-Picture (PIP) controller
all bits are reserved Preliminary specification
SAB9080
Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
MPIPON (DOUBLE WINDOW) Bit MPIPON is used to switch the main channel PIP on (logic 1) or off (logic 0). SPIPON Bit SPIPON is used to switch the subchannel PIPs on (logic 1) or off (logic 0). PRIO The priority bit decides whether the main channel PIP (Prio set to logic 0) or the subchannel PIP (Prio set to logic 1) will be on top when both PIPs overlap. S1FLD If S1FLD is set to logic 0, two fields are used for the live PIP. When a 50/60 Hz or a 60/50 Hz mode is detected, the SAB9080 automatically switches to the 1-Field mode (1-Field resolution vertically). If S1FLD is set to logic 1, only one field is used. This causes joint line errors but saves memory. This bit should not be set in normal modes. SFREEZE With SFreeze set to logic 1, the current live subchannel PIP will be frozen. If set to logic 0, it is unfrozen. ALGOFF In double window mode, precautions are taken to prevent a joint line error. Under some conditions, this feature should be switched off. This can be realized by setting this bit to logic 1. Normally, bit AlgOff should be set to logic 0. DNONINT In normal mode (this bit is logic 0), the SAB9080 calculates whether a signal is non-interlaced and reacts accordingly. With bit DNonint set to logic 1, the display channel is forced into the non-interlaced mode. In the non-interlaced mode, only one field is used during the processing of the PIPs. PIPMODE The PIP modes for the SAB9080 are shown in Table 2. Table 2 PIP modes MODE double window mode replay mode 9 SHRED AND SVRED (DOUBLE WINDOW)
SAB9080
Bits SHRed<5:0> and SVRed<6:0> determine the reduction factors in the double window mode. The horizontal reduction is equal to SHRed/96; the vertical reduction is equal to SVRed/96. SHRed should lie in the range from 0 to 48; if set to logic 0, the PIP is off. SVRed should lie in the range from 0 to 96; if set to logic 0, the PIP is off. When the horizontal reduction factor is 48/96), 704 samples are processed. The horizontal reduction is linear; therefore, when it is 24/96, 352 samples are processed. The same holds for the vertical reduction factor but then with the number of lines. For NTSC, the number of processed lines can be calculated from SVRed/96 x 228 lines. SHRED AND SVRED (REPLAY) In replay mode, the ranges of SHRed and SVRed are limited as follows: SHRed = 12; SVRed = 24, 16 or 12. This leads to a fixed horizontal reduction factor of 18; and to a variable vertical reduction factor of 14, 16 or 18. Note that the resulting replay PIP can be expanded by using SHBlow and/or SVBlow. BGHFP AND BGVFP These bits control the horizontal and vertical positioning of the PIP configuration on the screen. The horizontal range is adjustable in 16 steps of four 28 MHz clock periods. The vertical range is 16 steps of 1 line/field. The background colour can be adjusted with bits BSel, SBBrt and SBCol. SDHFP AND SDVFP These bytes control the horizontal and vertical positioning of the subchannel PIPs on the screen. The horizontal range is 256 steps of eight 28 MHz clock periods. The vertical range is 256 steps of 1 line/field. MAHFP, SAHFP AND SAVFP Bits MAHfp<3:0>, bits SAHfp<3:0> and byte SAVfp control the horizontal and vertical inset starting-points of the acquired data. The horizontal range is 16 steps of eight 28 MHz clock periods when SV2 is set to logic 1. When SV2 is set to logic 0, the horizontal range is
PipMode<2:0> 000 001 1999 Nov 12
Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
restricted to eight steps. The vertical range is 256 steps of 1 line/field. DUVPOL, DVSPOL, DFPOL AND DHSYNC These bits control the PLL/deflection settings. With DUVPol, the polarity of the border UV signals can be inverted when the deflection circuit after the SAB9080 expects inverted signals. With DVSPol set to logic 0, the SAB9080 triggers on positive edges of the DVSYNC. If DVSPol is set to logic 1, it triggers on negative edges. Bit DFPol can invert the field ID of the incoming fields. Bit DHsync determines the timing of the DHSYNC pulse. If it is set to logic 0, a burstkey is expected; if it is set to logic 1, a horizontal sync is expected at pin DHSYNC. SUVPOL, SVSPOL, SFPOL AND SHSYNC These bits control the PLL/decoder settings. With SUVPol, the polarity of the video UV signals can be inverted when the decoder circuit before the SAB9080 emits inverted signals. With SVSPol set to logic 0, the SAB9080 triggers on positive edges of the SVSYNC. If it is set to logic 1, it triggers on the negative edges. Bit SFPol can invert the field ID of the incoming fields. Bit SHsync determines the timing of the SHSYNC pulse. If it is set to logic 0, a burstkey is expected; if it is set to logic 1, a horizontal sync is expected at pin SHSYNC. MFIDPON AND SFIDPON Bits MFidPOn (main field identification position on) and SFidPOn (subfield identification position on) enable the field identification position fine tuning. The default value is off (logic 0), no fine positioning. When on (logic 1), the field identification position is determined by the value of bytes MainFidPos and SubFidPos. BGON Bit BGOn determines whether the background is visible. The background has a size of 720 pixels and 240 lines for NTSC. The background colour can be adjusted with bits BSel, SBBrt and SBCol. BON, SBBRT, SBCOL AND BSEL Bit BOn can switch the sub-borders on (logic 1) or off (logic 0). Bits SBBrt<1:0> and SBCol<2:0> set the brightness and colour type of the selected border. The brightness is set in four levels: 30%, 50%, 70% and
SAB9080
100% IRE. The colour type is one of black (grey), blue, red, magenta, green, cyan, yellow or white (grey). For black and white, a finer scale is available. Bits BSel<1:0> select which colour is set: background or border, see Table 3. Table 3 BSel modes BORDER COLOUR SET main sub background sub-border select
BSel<1:0> 00 01 10 11 MDHFP AND MDVFP
These bytes control the horizontal and vertical positioning of the main PIP on the screen. The horizontal range is 256 steps of eight 28 MHz clock periods. The vertical range is 256 steps of 1 line/field. MHRED Bits MHRed<5:0>, in a range from 0 to 48, determine the horizontal reduction factor MHRed/96. If they are set to logic 0, the PIP is off. If they are set to the maximum value of 48, the horizontal reduction factor is 0.5. SHBLOW AND SVBLOW (REPLAY MODE) Bits SHBlow<1:0> and bit SVBlow are used in the replay mode. These bits can expand a pixel on the display side by a factor two (01) or four (11) in the horizontal direction (SHBlow) and a factor of two (1) in the vertical direction (SVBlow). Zero values indicate no expansion. MHBLOW Bit MHBlow can expand the main picture by a factor of two in the horizontal direction. SLSEL (REPLAY MODE) In the replay PIP mode, bits SLSel<5:0> determine at which memory location the PIP data is written, the range depends on the memory usage for each PIP. The maximum number of PIPs that can be stored in NTSC mode is 42.
1999 Nov 12
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Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
SDSEL (REPLAY MODE) Bits SDSel<5:0> select which PIP is read from memory. Valid numbers are dependent on the maximum value of SLSel. SFBLKPKOFF Bits SFBlkPkOff<1:> shift signals FBL and PKOFF with respect to the YUV output, by half pixels, see Table 4. Table 4 Shifts of FBL and PKOFF SHIFT OF FBL AND PKOFF no shift +0.5 pixel -0.5 pixel -1 pixel NOTES HBWIDTH AND VBWIDTH SV2
SAB9080
When set to logic 0, bit SV2 limits the range of the MAHfp and SAHfp parameters. Otherwise (bit SV2 set to logic 1), the parameters have their maximum range (which is recommended).
SFBlkPkOff<1:0> 00 01 10 11 I2CHOLD
Bits HBWidth<2:0> and VBWidth<2:0>control the horizontal and vertical border sizes in steps of two pixels and one line. The default horizontal border size is four pixels and the vertical border size is two lines per field. Default means after power-up and no I2C-bus data sent to the PIP controller.
Bit I2CHold controls the updating of the I2C-bus controlled function towards the PIP. If set to logic 1, some updates are on hold until the bit is set to logic 0. At the next main Vsync, all settings are passed to the PIP functions. The bits and bytes that are on hold when bit I2CHold is set to logic 1 are: * MPIPON, SPIPON, DNonint and PipMode * SHBlow and SVBlow * SHRed and SVRed * BGHfp and BGVfp * SDHfp and SDVfp * SHPic and SVPic * BGOn, BOn and Prio * BSel, SBBrt and SBCol * SDSel * MDHfp and MDVfp * HBWidth and VBWidth. SV1 Bit SV1 controls the internal horizontal offset of the background. When set to logic 0, the offset is 0.86 s; when set to logic 1, the offset is 4.56 s.
1. When the input signals for the main and/or subchannel are non-interlaced, joint line errors can occur. When non-interlaced signals are input, the SAB9080 switches automatically to the non-interlaced mode. 2. When the prevent joint line error algorithm is switched off (AlgOff is set to logic 1), joint line errors can still occur in the 2-Field mode. Acquisition channel ADCs and clamping The analog input signals are converted to digital signals by three ADCs per channel. The resolution of the ADCs is 8 bits (DNL is 7 bits and INL is 6 bits) and the sampling is performed at the system clock frequency of 28 MHz for the Y input. A bias voltage (Vbias) is used to decouple the AC components on internal references. The inputs should be AC coupled and an internal clamp circuit (using external clamp capacitors) will clamp the input to a level derived internally from Vref(B)(MA/SA) for the luminance channels and, for the chrominance channels, to (Vref(T)(MA/SA) + Vref(B)(MA/SA))/2 + LSB/2. The clamping starts at the active edge of the burst key. Internal video buffers amplify the standard Y, U and V input signals to the correct ADC levels. PLL The PLL generates an internal system clock from the fHSYNC of 1792 x fHSYNC, which is approximately 28 MHz. DACs and video buffers The 28 MHz digital video signals are fed to the 8-bit DACs that produce the required analog video signals. The video buffers amplify these signals prior to being fed to the output to drive another device.
1999 Nov 12
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Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD Tstg Tamb Vesd Rth(j-a) Pmax supply voltage range storage temperature ambient temperature electrostatic discharge handling thermal resistance maximum power dissipation PARAMETER MIN. -0.5 -25 0 - - -
SAB9080
MAX. 5.0 +150 70 2 45 1.0 V C C
UNIT
kV K/W W
QUALITY SPECIFICATION In accordance with "SNW-FQ-611, Part E", dated 14 December 1992. ESD LEVELS The standard ESD specification is JEDEC Class II (2 kV Human Body Model, 200 V Machine Model) unless indicated otherwise. Table 5 ESD performance PIN 68 69 70 72 73 74 rest in range 1 to 17 rest in range 64 to 100 SYMBOL FBL PKOFF DVSYNC SVSYNC SCL SDA all other pins HUMAN BODY MODEL (V) 1000 1000 1000 1000 1000 1000 standard specification standard specification MACHINE MODEL (V)
1999 Nov 12
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Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
ANALOG CHARACTERISTICS VDDA = 3.3 V; VDDD = 3.3 V; Tamb = 25 C; unless otherwise specified. SYMBOL Supplies VDDA VSSA VDDA(max) VSSA(max) IDDD(q) IDDA(DP) IDDA(SP) IDDA(MA) IDDA(SA) IDDA(DA) IDDA(MF) IDDA(SF) IDDA(tot) IDDD(tot) Vref(T) Vref(B) ViY(p-p) Vi(V)(p-p) Vi(U)(p-p) Ii Ci fsample RES DNL INL cs Vclamp(Y) Vclamp(U,V) positive supply voltage ground voltage maximum DC difference between supply voltages maximum DC difference between ground voltages quiescent current of digital supply voltages display PLL supply current sub-PLL supply current main ADCs supply current sub-ADCs supply current DACs supply current main buffers supply current sub-buffers supply current total analog supply current total digital supply current note 2 note 2 note 2 note 1 3.0 - - - - - - 60 60 8 4 4 140 - note 3 note 3 note 4 note 4 note 4 clamping off clamping on input capacitance sample frequency resolution differential non-linearity integral non-linearity channel separation Y clamping voltage level U/V clamping voltage level note 6 note 7 note 5 2.70 0.95 - - - - - - - 8 -1.4 -2.0 - 1.25 1.80 3.3 0 0 0 0 0.4 0.4 70 70 10 6 6 165 50 3.6 - 100 100 50 - - 90 90 12 9 9 210 - PARAMETER CONDITIONS MIN. TYP.
SAB9080
MAX.
UNIT
V V mV mV A mA mA mA mA mA mA mA mA mA
Analog-to-digital converter and clamping top reference voltage bottom reference voltage Y input signal amplitude (peak-to-peak value) V input signal amplitude (peak-to-peak value) U input signal amplitude (peak-to-peak value) input current 2.82 1.07 1.00 1.05 1.33 0.1 55 5 1792 x fHSYNC 8 - - 48 1.34 1.93 2.95 1.20 1.04 1.10 1.38 - - - - 8 +1.4 +2.0 - 1.45 2.15 V V V V V A A pF kHz bit LSB LSB dB V V
1999 Nov 12
13
Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
SAB9080
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital-to-analog converter and output stage Vref(T) Vref(B) RL CL fsample RES DNL INL cs fi(PLL) fi(subPLL) Notes 1. Digital clocks are silent, input pins POR and TM are connected to VDDA. 2. This value is measured with an external bias resistor of 39 k, resulting in a bias current of 55 A. 3. Voltages Vref(T) and Vref(B) are made by a resistor division of VDDA. They can be calculated with the formulas: 2.82 1.07 V ref(T) = V DDA x ------------------------ V and V ref(B) = V DDA x ------------------------ V . V DDA(nom) V DDA(nom) 4. The input signals are amplified to meet an internal peak-to-peak voltage level of 0.8 x (Vref(T) - Vref(B)), which equals the internal ADC input range. 5. The internal system clock frequency is 1792 x fHSYNC of the input channel. 6. The clamp level is not equal to the Vref(B) of the ADCs. V ref ( B ) + V ref ( T ) + V LSB 7. The UV channels are clamped to: ----------------------------------------------------------- . 2 8. The internal system clock frequency is 1792 x fHSYNC of the main channel. top reference voltage bottom reference voltage load resistance load capacitance sample frequency resolution differential non-linearity integral non-linearity channel separation note 8 1.10 0.15 1 0 - 8 -1.0 -1.0 - NTSC 14 1.20 0.23 - - 1792 x fHSYNC 8 - - 48 1.30 0.30 1000 5 - 8 +1.0 +1.0 - 17 V V k pF kHz bit LSB LSB dB
Display PLL and clock generation input frequency 15.75 kHz
sub-PLL and clock generation input frequency NTSC 14 15.75 17 kHz
1999 Nov 12
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Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
DIGITAL CHARACTERISTICS VDDA = 3.3 V; VDDD = 3.0 to 3.6 V; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. - 0.8VDDD 0.8VDDD 0.8VDDD default -0.5 0.8 - - TYP.
SAB9080
MAX.
UNIT
DC characteristics VIH HIGH-level input voltage default pin 74 5 V tolerant pins 68, 69, 70, 72, 73 VIL Vhys VOH VOL LOW-level input voltage hysteresis voltage HIGH-level output voltage IOH = -X mA; VDDD = 3.0 V; note 2 LOW-level output voltage IOL = X mA; VDDD = 3.0 V; note 2 IOL = 2 mA; VDDD = 3.0 V |ILI| |IOZ| Ilu(I/O) Rpu fclk(sys) tr tf Notes 1. The absolute maximum input voltage is 6.0 V. 2. X is the source/sink current under worst case conditions. X is reflected in the name of the I/O cell according to the drive capability. The minimum value of X is 1 mA. 3. The internal system clock frequency is 1792 x fHSYNC of the main channel and subchannel. input leakage current 3-state output leakage current I/O latch-up current internal pull-up resistor VI = 0 V VI = VDDD VO = 0 V or VO = VDDD V < 0 V; V > VDDD VDDD + 0.5 V 5.5(1) 5.5(1) 0.2VDDD - - 0.4 0.4 1 1 1 - 78 - 25 25 V V V V V V V A A A mA k
0.85VDDD - - - - - - 200 16 - - - - - - - - - 33 1792 x fHSYNC 6 6
AC characteristics system clock frequency rise time fall time note 3 kHz ns ns
1999 Nov 12
15
Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
TEST AND APPLICATION INFORMATION
SAB9080
Figure 4 gives the application diagram in a standard configuration. Input signals main channel CVBS and subchannel CVBS from different video sources are processed by the SAB9080 and inserted by the YUV to RGB switch.
handbook, full pagewidth
HS/VS FBL SUB DECODER
subchannel CVBS
YUV
TDA8310
YUV
SAB9080
PIP CONTROLLER
YUV to RGB SWITCH
RGB
HS/VS
TDA4780
YUV/RGB PROCESSING AND DEFLECTION CIRCUIT RGB
HS/VS main channel CVBS MAIN DECODER
HS/VS
YUV
YUV
TDA8310
MGM811
Fig.4 Application diagram.
1999 Nov 12
16
Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
PACKAGE OUTLINE QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SAB9080
SOT317-2
c
y X
80 81
51 50 ZE
A
e E HE A A2 A1 (A 3) Lp bp 100 1 wM D HD ZD B vM B 30 vMA 31 detail X L
wM pin 1 index
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.20 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.40 0.25 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.65 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.15 y 0.1 Z D (1) Z E(1) 0.8 0.4 1.0 0.6 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT317-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
1999 Nov 12
17
Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
SAB9080
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1999 Nov 12
18
Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable suitable(2) recommended(3)(4) recommended(5) suitable not not suitable suitable suitable suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not
SAB9080
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 Nov 12
19
Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAB9080
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1999 Nov 12
20
Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
NOTES
SAB9080
1999 Nov 12
21
Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
NOTES
SAB9080
1999 Nov 12
22
Philips Semiconductors
Preliminary specification
NTSC Picture-In-Picture (PIP) controller
NOTES
SAB9080
1999 Nov 12
23
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 68
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545004/25/02/pp24
Date of release: 1999
Nov 12
Document order number:
9397 750 06141


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